As integrated circuits become more complex, it is becoming common to analyse them using simulation programs during the design phase rather than building test circuits. One way of analysing a circuit is to use a spice simulation wherein the circuit is simulated and its operation verified. A spice simulation will simulate the current through each element and the charge at each node and as such provides an accurate simulation but is computationally expensive, prohibitively so for large circuits.
Complex circuits are now commonly built from standard cells that perform particular functions within a circuit and are designed to fit within certain standard placement areas. These cells are coupled together to form the complex circuit. Each of these standard cells are supplied with a characterisation file, which may be in the form of a liberty file, and provides characteristic information about the cell that has been derived from a spice simulation of the cell. This file will have lookup tables that indicate the delay time or the output transition time of the standard cell for different input transition times and different loadings.
A standard cell may perform a more or less complex logical function. Simple cells (examples are inverter, NAND, NOR) are formed of a single inverting stage between the input, or one of the inputs, (NAND and NOR have several inputs) and the output. Complex cells are formed by stacking several inverting stages between the input, or one of the inputs, and the output (examples are AND, OR, latch, flip-flop).
When a circuit is designed using standard cells, it can be analysed in a computationally efficient way by using static timing analysis that makes use of these liberty files. Thus, signal paths within the circuit are identified and the loading on a first cell in the signal path is determined from the cells connected to it, and then using the input signal to determine the input transition time the delay time and the output transition time are determined from the lookup tables. The output transition time can then be used as the input transition time for the next cell in the path and the delay and the output transition time can be determined for this cell. In this way a timing delay for a path can be determined.
One problem with static timing analysis is that the characterisation files for the cells are the characteristics of the cells that have been determined for the cell with particular predetermined loadings and not for the cell when it is in situ in the circuit currently being analysed. Thus, although the cells may have had similar capacitive loads attached to them during simulation, these loads were not the devices of the circuit through which data signals are actually being sent. Thus, the simulation does not have taken account of the reverse Miller effect. The reverse Miller effect is a capacitive coupling effect, where an output transition of a CMOS stage will slow down the input transition due to the capacitive coupling between the two. The Miller capacitance of a cell is the capacitance between the input and the output including the CMOS transistors and additional parasitic capacitances.
FIG. 1 shows two example cells, a simple cell having an inverter circuit and a more complex cell that is formed of two inverter stages. In the simple cell and the first inverting stage of the more complex cell the output signal is switching in the opposite direction to the input signal, the input signal is reduced in magnitude by the output signal through the capacitive coupling between input and output. The consequence of this is that the input signal switches more slowly and the actual delay of the cell is larger than would be the case without the reverse Miller effect.
A problem with static timing analysis is that as the cells are characterised as standard cells with hypothetical loads the reverse Miller effect due to other components in the circuit affecting the input signal cannot be allowed for as the actual arrangement of the final circuit is not known at the time that the characterisation files are generated.
One way of addressing this problem has been to identify, using static timing analysis, which paths are the critical paths within a complex circuit and then just these paths can be analysed using spice simulation to check the accuracy of the static timing analysis for this subset of important paths.
It would be desirable to be able to analyse complex circuits accurately without too large a computational burden.